東華大學圖書館 |

語系: 繁體中文

說明(常見問題)

回圖書館首頁

手機版館藏查詢

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

Modeling, synthesis, and rapid proto...

~

Ciletti, Michael D.

FindBook

Google Book

Amazon

博客來

Modeling, synthesis, and rapid prototyping with the Verilog HDL /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Modeling, synthesis, and rapid prototyping with the Verilog HDL // Michael D. Ciletti.
作者:	Ciletti, Michael D.
出版者:	Upper Saddle River, N.J. :Prentice Hall, : c1999.,
面頁冊數:	xxii, 727 p. :ill. ;25 cm.
標題:	Verilog (Computer hardware description language). -
ISBN:	0139773983 (pbk.) :

Modeling, synthesis, and rapid prototyping with the Verilog HDL /
Ciletti, Michael D.

Modeling, synthesis, and rapid prototyping with the Verilog HDL /Michael D. Ciletti. - Upper Saddle River, N.J. :Prentice Hall,c1999. - xxii, 727 p. :ill. ;25 cm.

Includes bibliographical references and index.

ISBN: 0139773983 (pbk.) :NT4012

LCCN: 99010494Subjects--Topical Terms:

750071
Verilog (Computer hardware description language).

LC Class. No.: TK7885.7 / .C55 1999

Dewey Class. No.: 621.392

Modeling, synthesis, and rapid prototyping with the Verilog HDL /
LDR:00586cam 2200181 a 4500 001 2188548
005 20071211170027.0
008 200310s1999 njua b 001 0 eng
010 $a 99010494
020 $a 0139773983 (pbk.) : $c NT4012
035 $a 00994917
040 $a DLC $c DLC $d WaU $d NCTU
042 $a pcc
050 0 0 $a TK7885.7 $b .C55 1999
082 0 0 $a 621.392 $2 21
100 1 $a Ciletti, Michael D. $3 1048021
245 1 0 $a Modeling, synthesis, and rapid prototyping with the Verilog HDL / $c Michael D. Ciletti.
260 # $a Upper Saddle River, N.J. : $b Prentice Hall, $c c1999.
300 $a xxii, 727 p. : $b ill. ; $c 25 cm.
504 $a Includes bibliographical references and index.
650 # 0 $a Verilog (Computer hardware description language). $3 750071
650 # 0 $a Rapid prototyping. $3 820011

筆 0 讀者評論

館藏地: 出版年: 卷號:

館藏

1 筆 • 頁數 1 •
1

典藏地名稱

館藏流通類別

GW0022510

六樓西文書區HC-Z(6F Western Language Books)

01.外借(書)_YB

一般圖書

TK7885.7 C55 1999

一般使用(Normal)

在架

0

1 筆 • 頁數 1 •
1

評論

新增評論分享你的心得

Export

取書館

變更密碼

登入