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Behavioral synthesis for hardware se...

Katkoori, Srinivas.

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Behavioral synthesis for hardware security

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Behavioral synthesis for hardware security/ edited by Srinivas Katkoori, Sheikh Ariful Islam.
其他作者:	Katkoori, Srinivas.
出版者:	Cham :Springer International Publishing : : 2022.,
面頁冊數:	xv, 398 p. :ill., digital ;24 cm.
內容註:	Introduction -- Background -- Techniques for algorithm-level obfuscation during high-level synthesis -- High-level synthesis of key based obfuscated RTL datapaths -- RTL Hardware IP protection Using Key-Based Control and Data Flow Obfuscation -- Empirical Word-Level Analysis of Arithmetic Module Architectures for Hardware Trojan Susceptibility -- Behavioral synthesis techniques for intellectual property protection -- Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis -- High-Level Synthesis for Side-Channel Defense -- On state encoding against power analysis attacks for finite state controllers -- Examining the consequences of high-level synthesis optimizations on power side-channel -- Towards a timing attack aware high-level synthesis of integrated circuits -- High-Level Synthesis with Timing-Sensitive Information Flow Enforcement -- Mitigating information leakage during critical communication using S*FSM -- Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security-Driven Task Scheduling -- Securing industrial control system with high level synthesis -- Conclusions and open research problems.
Contained By:	Springer Nature eBook
標題:	Integrated circuits - Security measures. -
電子資源:	https://doi.org/10.1007/978-3-030-78841-4
ISBN:	9783030788414

Behavioral synthesis for hardware security
Behavioral synthesis for hardware security[electronic resource] /edited by Srinivas Katkoori, Sheikh Ariful Islam. - Cham :Springer International Publishing :2022. - xv, 398 p. :ill., digital ;24 cm.

Introduction -- Background -- Techniques for algorithm-level obfuscation during high-level synthesis -- High-level synthesis of key based obfuscated RTL datapaths -- RTL Hardware IP protection Using Key-Based Control and Data Flow Obfuscation -- Empirical Word-Level Analysis of Arithmetic Module Architectures for Hardware Trojan Susceptibility -- Behavioral synthesis techniques for intellectual property protection -- Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis -- High-Level Synthesis for Side-Channel Defense -- On state encoding against power analysis attacks for finite state controllers -- Examining the consequences of high-level synthesis optimizations on power side-channel -- Towards a timing attack aware high-level synthesis of integrated circuits -- High-Level Synthesis with Timing-Sensitive Information Flow Enforcement -- Mitigating information leakage during critical communication using S*FSM -- Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security-Driven Task Scheduling -- Securing industrial control system with high level synthesis -- Conclusions and open research problems.

This book presents state-of-the-art research results from leading electronic design automation (EDA) researchers on automated approaches for generating cyber-secure, smart hardware. The authors first provide brief background on high-level synthesis principles and motivate the need for secure design during behavioral synthesis. Then they provide readers with synthesis techniques for six automated security solutions, namely, hardware obfuscation, hardware Trojan detection, IP watermarking, state encoding, side channel attack resistance, and information flow tracking. Provides a single-source reference to behavioral synthesis for hardware security; Describes automatic synthesis techniques for algorithmic obfuscation, using code transformations; Includes behavioral synthesis techniques for intellectual property protection.

ISBN: 9783030788414

Standard No.: 10.1007/978-3-030-78841-4doiSubjects--Topical Terms:

3308545
Integrated circuits
--Security measures.

LC Class. No.: TK7874 / .B44 2022

Dewey Class. No.: 621.3815

Behavioral synthesis for hardware security
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505 0 $a Introduction -- Background -- Techniques for algorithm-level obfuscation during high-level synthesis -- High-level synthesis of key based obfuscated RTL datapaths -- RTL Hardware IP protection Using Key-Based Control and Data Flow Obfuscation -- Empirical Word-Level Analysis of Arithmetic Module Architectures for Hardware Trojan Susceptibility -- Behavioral synthesis techniques for intellectual property protection -- Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis -- High-Level Synthesis for Side-Channel Defense -- On state encoding against power analysis attacks for finite state controllers -- Examining the consequences of high-level synthesis optimizations on power side-channel -- Towards a timing attack aware high-level synthesis of integrated circuits -- High-Level Synthesis with Timing-Sensitive Information Flow Enforcement -- Mitigating information leakage during critical communication using S*FSM -- Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security-Driven Task Scheduling -- Securing industrial control system with high level synthesis -- Conclusions and open research problems.
520 $a This book presents state-of-the-art research results from leading electronic design automation (EDA) researchers on automated approaches for generating cyber-secure, smart hardware. The authors first provide brief background on high-level synthesis principles and motivate the need for secure design during behavioral synthesis. Then they provide readers with synthesis techniques for six automated security solutions, namely, hardware obfuscation, hardware Trojan detection, IP watermarking, state encoding, side channel attack resistance, and information flow tracking. Provides a single-source reference to behavioral synthesis for hardware security; Describes automatic synthesis techniques for algorithmic obfuscation, using code transformations; Includes behavioral synthesis techniques for intellectual property protection.
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