語系:
繁體中文
English
說明(常見問題)
回圖書館首頁
手機版館藏查詢
登入
回首頁
到查詢結果
[ subject:"Logic Design." ]
切換:
標籤
|
MARC模式
|
ISBD
Digital logic design using Verilog =...
~
Taraate, Vaibbhav.
FindBook
Google Book
Amazon
博客來
Digital logic design using Verilog = coding and RTL synthesis /
紀錄類型:
書目-電子資源 : Monograph/item
正題名/作者:
Digital logic design using Verilog/ by Vaibbhav Taraate.
其他題名:
coding and RTL synthesis /
作者:
Taraate, Vaibbhav.
出版者:
Singapore :Springer Singapore : : 2022.,
面頁冊數:
xxv, 604 p. :ill., digital ;24 cm.
內容註:
Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs.
Contained By:
Springer Nature eBook
標題:
Logic design - Data processing. -
電子資源:
https://doi.org/10.1007/978-981-16-3199-3
ISBN:
9789811631993
Digital logic design using Verilog = coding and RTL synthesis /
Taraate, Vaibbhav.
Digital logic design using Verilog
coding and RTL synthesis /[electronic resource] :by Vaibbhav Taraate. - Second edition. - Singapore :Springer Singapore :2022. - xxv, 604 p. :ill., digital ;24 cm.
Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs.
This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists.
ISBN: 9789811631993
Standard No.: 10.1007/978-981-16-3199-3doiSubjects--Topical Terms:
649530
Logic design
--Data processing.
LC Class. No.: TK7868.L6 / T37 2022
Dewey Class. No.: 621.395
Digital logic design using Verilog = coding and RTL synthesis /
LDR
:02184nmm a2200337 a 4500
001
2296026
003
DE-He213
005
20211031193333.0
006
m d
007
cr nn 008maaau
008
230324s2022 si s 0 eng d
020
$a
9789811631993
$q
(electronic bk.)
020
$a
9789811631986
$q
(paper)
024
7
$a
10.1007/978-981-16-3199-3
$2
doi
035
$a
978-981-16-3199-3
040
$a
GP
$c
GP
041
0
$a
eng
050
4
$a
TK7868.L6
$b
T37 2022
072
7
$a
TJFC
$2
bicssc
072
7
$a
TEC008010
$2
bisacsh
072
7
$a
TJFC
$2
thema
082
0 4
$a
621.395
$2
23
090
$a
TK7868.L6
$b
T176 2022
100
1
$a
Taraate, Vaibbhav.
$3
2195158
245
1 0
$a
Digital logic design using Verilog
$h
[electronic resource] :
$b
coding and RTL synthesis /
$c
by Vaibbhav Taraate.
250
$a
Second edition.
260
$a
Singapore :
$b
Springer Singapore :
$b
Imprint: Springer,
$c
2022.
300
$a
xxv, 604 p. :
$b
ill., digital ;
$c
24 cm.
505
0
$a
Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs.
520
$a
This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists.
650
0
$a
Logic design
$x
Data processing.
$3
649530
650
0
$a
Verilog (Computer hardware description language)
$3
709274
650
1 4
$a
Circuits and Systems.
$3
896527
650
2 4
$a
Electronics and Microelectronics, Instrumentation.
$3
893838
650
2 4
$a
Logic Design.
$3
892735
710
2
$a
SpringerLink (Online service)
$3
836513
773
0
$t
Springer Nature eBook
856
4 0
$u
https://doi.org/10.1007/978-981-16-3199-3
950
$a
Engineering (SpringerNature-11647)
筆 0 讀者評論
館藏地:
全部
電子資源
出版年:
卷號:
館藏
1 筆 • 頁數 1 •
1
條碼號
典藏地名稱
館藏流通類別
資料類型
索書號
使用類型
借閱狀態
預約狀態
備註欄
附件
W9437929
電子資源
11.線上閱覽_V
電子書
EB TK7868.L6 T37 2022
一般使用(Normal)
在架
0
1 筆 • 頁數 1 •
1
多媒體
評論
新增評論
分享你的心得
Export
取書館
處理中
...
變更密碼
登入