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Patterns for time-triggered embedded...

Pont, Michael J

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Patterns for time-triggered embedded systems : = building reliable applications with the 8051 family of microcontrollers /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Patterns for time-triggered embedded systems :/ Michael J. Pont
其他題名:	building reliable applications with the 8051 family of microcontrollers /
作者:	Pont, Michael J
出版者:	Harlow :Addison-Wesley, : 2001,
面頁冊數:	xxiii, 1,000 pages :illustrations ;25 cm
標題:	Software engineering - Congresses. -
ISBN:	0201331381

Patterns for time-triggered embedded systems : = building reliable applications with the 8051 family of microcontrollers /
Pont, Michael J

Patterns for time-triggered embedded systems :building reliable applications with the 8051 family of microcontrollers /Michael J. Pont - Harlow :Addison-Wesley,2001 - xxiii, 1,000 pages :illustrations ;25 cm

Includes bibliographical references and index

What is a time-triggered embedded system?1

CD-ROM contains: Source code in 'C' for patterns and examples -- Evaluation version of the industry-standard Keil 'C' compiler and hardware simulator

One CD-ROM attached at back of book

ISBN: 0201331381Subjects--Topical Terms:

696781
Software engineering
--Congresses.

LC Class. No.: TK7895.E42 / P66 2001

Dewey Class. No.: 005.117

Patterns for time-triggered embedded systems : = building reliable applications with the 8051 family of microcontrollers /
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245 1 0 $a Patterns for time-triggered embedded systems : $b building reliable applications with the 8051 family of microcontrollers / $c Michael J. Pont
260 # $a Harlow : $b Addison-Wesley, $c 2001
300 $a xxiii, 1,000 pages : $b illustrations ; $c 25 cm
504 $a Includes bibliographical references and index
505 0 0 $g 1 $t What is a time-triggered embedded system? $g 3 -- $g 1.2 $t Information systems $g 3 -- $g 1.3 $t Desktop systems $g 5 -- $g 1.4 $t Real-time systems $g 6 -- $g 1.5 $t Embedded systems $g 8 -- $g 1.6 $t Event-triggered systems $g 10 -- $g 1.7 $t Time-triggered systems $g 11 -- $g 2 $t Designing embedded systems using patterns $g 15 -- $g 2.2 $t Limitations of existing software design techniques $g 17 -- $g 2.3 $t Patterns $g 22 -- $g 2.4 $t Patterns for time-triggered systems $g 24 -- $g Part $t A Hardware foundations $g 27 -- $g 3 $t 8051 microcontroller family $g 29 -- $t Standard 8051 $g 30 -- $t Small 8051 $g 41 -- $t Extended 8051 $g 46 -- $g 4 $t Oscillator hardware $g 53 -- $t Crystal Oscillator $g 54 -- $t Ceramic Resonator $g 64 -- $g 5 $t Reset hardware $g 67 -- $t Rc Reset $g 68 -- $t Robust Reset $g 77 -- $g 6 $t Memory issues $g 81 -- $t On-Chip Memory $g 82 -- $t Off-Chip Data Memory $g 94 -- $t Off-Chip Code Memory $g 100 -- $g 7 $t Driving DC loads $g 109 -- $t Naked Led $g 110 -- $t Naked Load $g 115 -- $t IC Buffer $g 118 -- $t BJT Driver $g 124 -- $t IC Driver $g 134 -- $t Mosfet Driver $g 139 -- $t SSR Driver (DC) $g 144 -- $g 8 $t Driving AC loads $g 148 -- $t Emr Driver $g 149 -- $t SSR Driver (AC) $g 156 -- $g Part B $t Software foundations $g 159 -- $g 9 $t A rudimentary software architecture $g 161 -- $t Super Loop $g 162 -- $t Project Header $g 169 -- $g 10 $t Using the ports $g 173 -- $t Port I/O $g 174 -- $t Port Header $g 184 -- $g 11 $t Delays $g 193 -- $t Hardware Delay $g 194 -- $t Software Delay $g 206 -- $g 12 $t Watchdogs $g 215 -- $t Hardware Watchdog $g 217 -- $g Part C $t Time-triggered architectures for single-processor systems $g 229 -- $g 13 $t An introduction to schedulers $g 231 -- $g 13.2 $t Desktop OS $g 231 -- $g 13.3 $t Assessing the super loop architecture $g 233 -- $g 13.4 $t A better solution $g 235 -- $g 13.5 $t Example: Flashing an LED $g 239 -- $g 13.6 $t Executing multiple tasks at different time intervals $g 243 -- $g 13.7 $t What is a scheduler? $g 245 -- $g 13.8 $t Co-operative and pre-emptive scheduling $g 246 -- $g 13.9 $t A closer look at pre-emptive schedulers $g 250 -- $g 14 $t Co-operative schedulers $g 254 -- $g 15 $t Learning to think co-operatively $g 297 -- $t Loop Timeout $g 298 -- $t Hardware Timeout $g 305 -- $g 16 $t Task-oriented design $g 316 -- $t Multi-Stage Task $g 317 -- $t Multi-State Task $g 322 -- $g 17 $t Hybrid schedulers $g 332 -- $t Hybrid Scheduler $g 333 -- $g Part D $t User interface $g 359 -- $g 18 $t Communicating with PCs via RS-232 $g 361 -- $t PC Link (RS-232) $g 362 -- $g 19 $t Switch interfaces $g 397 -- $t Switch Interface (Software) $g 399 -- $t Switch Interface (Hardware) $g 410 -- $t On-Off Switch $g 414 -- $t Multi-State Switch $g 423 -- $g 20 $t Keypad interfaces $g 433 -- $g 21 $t Multiplexed LED displays $g 449 -- $t Mx Led Display $g 450 -- $g 22 $t Controlling LCD panels $g 465 -- $t LCD Character Panel $g 467 -- $g Part E $t Using serial peripherals $g 491 -- $g 23 $t Using 'I[superscript 2]C' peripherals $g 493 -- $t I[superscript 2]C Peripheral $g 494 -- $g 24 $t Using 'SPI' peripherals $g 520 -- $t SPI Peripheral $g 521 -- $g Part F $t Time-triggered architectures for multiprocessor systems $g 537 -- $g 25 $t An introduction to shared-clock schedulers $g 539 -- $g 25.2 $t Additional CPU performance and hardware facilities $g 539 -- $g 25.3 $t Benefits of modular design $g 541 -- $g 25.4 $t How do we link more than one processor $g 543 -- $g 25.5 $t Why additional processors may not always improve reliability $g 550 -- $g 26 $t Shared-clock schedulers using external interrupts $g 553 -- $t SCI Scheduler (Tick) $g 554 -- $t SCI Scheduler (Data) $g 593 -- $g 27 $t Shared-clock schedulers using the UART $g 608 -- $t SCU Scheduler (Local) $g 609 -- $t SCU Scheduler (RS-232) $g 642 -- $t SCU Scheduler (RS-485) $g 646 -- $g 28 $t Shared-clock schedulers using CAN $g 675 -- $t SCC Scheduler $g 677 -- $g 29 $t Designing multiprocessor applications $g 711 -- $t Data Union $g 712 -- $t Long Task $g 716 -- $t Domino Task $g 720 -- $g Part G $t Monitoring and control components $g 725 -- $g 30 $t Pulse-rate sensing $g 727 -- $t Hardware Pulse Count $g 728 -- $t Software Pulse Count $g 736 -- $g 31 $t Pulse-rate modulation $g 741 -- $t Hardware PRM $g 742 -- $t Software PRM $g 748 -- $g 32 $t Using analogue-to-digital converters (ADCs) $g 756 -- $t One-Shot ADC $g 757 -- $t ADC Pre-Amp $g 777 -- $t Sequential ADC $g 782 -- $t A-A Filter $g 794 -- $t Current Sensor $g 802 -- $g 33 $t Pulse-width modulation2 $g 807 -- $t Hardware PWM $g 808 -- $t PWM Smoother $g 818 -- $t 3-Level PWM $g 822 -- $t Software PWM $g 831 -- $g 34 $t Using digital-to-analog converters (DACs) $g 840 -- $t DAC Output $g 841 -- $t DAC Smoother $g 853 -- $t DAC Driver $g 857 -- $g 35 $t Taking control $g 860 -- $t PID Controller $g 861 -- $g Part H $t Specialized time-triggered architectures $g 891 -- $g 36 $t Reducing the system overheads $g 893 -- $t 255-Tick Scheduler $g 894 -- $t One-Task Scheduler $g 911 -- $t One-Year Scheduler $g 919 -- $g 37 $t Increasing the stability of the scheduling $g 931 -- $t Stable Scheduler $g 932 -- $g 39.3 $t Design techniques for real-time/embedded systems $g 952 -- $g 39.4 $t Design techniques for high-reliability systems $g 953 -- $g 39.5 $t 8051 microcontroller $g 954 -- $t A Design notation and CASE tool $g 957 -- $t CASE tool $g 957 -- $t Notation $g 957 -- $g B $t Guide to the CD $g 980
520 # $a CD-ROM contains: Source code in 'C' for patterns and examples -- Evaluation version of the industry-standard Keil 'C' compiler and hardware simulator
525 $a One CD-ROM attached at back of book
650 # 0 $a Software engineering $x Congresses. $3 696781
650 # 0 $a Embedded computer systems $x Programming $3 2423008
650 # 0 $a Intel 8051 (Microcontroller) $3 2069806
650 # 4 $a architecture à activation temporelle $3 3624666
650 # 4 $a microcontrôleur $3 3624667
650 # 4 $a 8051 $3 3624668
650 # 4 $a système embarqué $3 3624669